Snap HDL

What is Snap HDL?

Snap HDL™ is a hardware description language for designing the digital hardware in logic devices such as FPGAs and ASICs. The language is based on C/C++ and is an alternative to Verilog or VHDL. It can be used for designs of any complexity.

The unit of design is a module which corresponds to a module in Verilog or an entity architecture pair in VHDL. As in other HDLs, modules may be combined into a design hierarchy.

A Snap HDL design is predictable and deterministic. Every register is specified explicitly so the behaviour of a design from clock cycle to clock cycle is fully predictable and controllable.

A design written in Snap HDL may be directly simulated by compiling it with a C++ compiler and linking it with a test harness which is typically written in C or C++. Simulation is fast because the structures which support simulation are extremely efficient.

For synthesis, a converter tool transforms a design in Snap HDL into its equivalent representation in Verilog or VHDL. A conventional synthesis flow can then be used to target a device such as an FPGA or ASIC.

Why use Snap HDL?

Snap HDL is simple to learn and use. Most of the language, such as "if" statements, "for" loops and variable assignments will be familiar to anyone with a basic knowledge of the C language. Snap HDL introduces a small set of special keywords to represent hardware features such D-type flip-flops and modules. Designs written in Snap HDL are often more concise that designs written in other HDLs.

The entire Snap HDL language is synthesizable with the exception of a small number of constructs which control simulation. So if a design is written according to the language rules it will synthesize.

Snap HDL supports modern development practices by making it easy to test a hardware design as part of a standard system build process.

Who is Snap HDL for?

Snap HDL is for hardware engineers who wish to improve their productivity while maintaining control over all aspects of a hardware design.

Snap HDL is for software engineers who wish to leverage their existing knowledge of C/C++ and apply it to hardware design. The full power of C++ can be used when simulating a design.

Snap HDL is for project managers who want their software and hardware teams to be more integrated and share in the development and testing of hardware designs.

When is Snap HDL available?

Snap HDL is coming soon! Contact us now if you would like more details when they become available.